In semiconductor manufacturing process, a flat wafer surface is very important for semiconductor devices towards high compactness and density. The conventional method for planarizing wafer surface is a chemical mechanical polishing method. In this method, a polishing slurry is added between a wafer surface and a polishing pad, and mechanical forces and chemical reactions between the polishing slurry and the wafer surface are taken advantage of to planarize the wafer surface. The conventional chemical mechanical polishing method is a dissociation abrasive polishing method. In the dissociation abrasive polishing method, an abrasive in a polishing slurry is distributed randomly on a polishing pad, which induces many problems such as an uneven density, a poor polishing result, a low utilization ratio of the polishing slurry and environmental pollution caused by the dumped polishing slurry. Therefore, the dissociation abrasive polishing method is gradually replaced by a fixed abrasive polishing method.
In the fixed abrasive polishing method, an abrasive and a polishing pad are combined together to form a fixed abrasive pad with a regular concave-convex surface. Referring to FIG. 1, a conventional fixed abrasive polishing method, as known in the prior art, includes conveying a polishing pad 102 to a polishing platen 101 by an input roller 105a and an output roller 105b, wetting the surface of the polishing pad 102 by a polishing slurry, and mounting a wafer 103 to a polishing chuck 104 so that the wafer surface contacts the abrasive layer of the polishing pad 102. The method further includes starting a driving power to rotate the polishing platen 101 by rotary driving of a bearing 100 and to rotate the wafer 103 by rotary driving of a polishing head 104, which make the polishing platen 101 and the wafer 103 rotate in opposite directions so that the surface of the wafer 103 is polished by the abrasive layer of the polishing pad 102. In this polishing process, a contact area between the polishing pad and the wafer is smaller than that in the conventional dissociation abrasive polishing method because only abrasive blocks of the polishing pad 102 contacts the surface of the wafer 103, so that there is a greater pressure force in the contact area. Accordingly, to a large extent, the polishing speed and efficiency are improved and the process window of erosion is broadened, which reduces the erosion and dishing problems greatly and enhances the product yield. Moreover, because the polishing speed has a high selectivity to the surface topography of the wafer, a desired polishing effect can be achieved by a less removal, which further reduces the production cost. With the continuous development of semiconductor manufacturing technology, and the continuous scaling down of the critical dimensions of semiconductor devices, the fixed abrasive polishing method has become more and more important.
To solve problems caused by devices with small critical dimensions, a technology combining a high-k gate dielectric layer and a metal gate is introduced into the manufacturing process of MOS transistors.
Referring to FIG. 2 to FIG. 6, which are schematic cross-sectional views illustrating a method for forming a high-k dielectric metal gate, as known in the prior art. the method includes:
Step S1, referring to FIG. 2: forming a dummy gate structure on a semiconductor substrate (not shown in the drawing), wherein the dummy gate structure includes a sacrificial oxide layer 201 and a polysilicon layer 202 covering the sacrificial oxide layer 201; forming spacers 203 around the dummy gate structure, wherein the spacers 203 may include silicon dioxide; and forming a silicon nitride layer 204 and a dielectric layer 205 covering the silicon nitride layer in sequence, wherein the dielectric layer 205 may include silicon dioxide and the silicon nitride layer 204 covers the polysilicon layer 202, the spacers 203 and the substrate;
Step S2, referring to FIG. 3, polishing the dielectric layer 205 until the silicon nitride layer 204 is exposed;
Step S3, referring to FIG. 4, polishing the silicon nitride layer 204 and the dielectric layer 205 until the polysilicon layer 202 is exposed;
Step S4, referring to FIG. 5, forming an opening 206 after etching and removing the dummy gate structure (the sacrificial oxide layer 201 and the polysilicon layer 202); and
Step S5, referring to FIG. 6, forming a gate dielectric layer 200 and a metal gate 207 successively in the opening 206, wherein the gate dielectric layer 200 may include high-k materials and the metal gate 207 may include aluminum or ruthenium.
The polishing processes described in the step S2 and step S3 are conducted continuously. Because the conventional dissociation abrasive polishing method can't achieve a desired surface flatness and uniformity, the fixed abrasive polishing method is generally applied to polishing processes nowadays. However, although the fixed abrasive polishing method can achieve a high flatness in the step S2, it induces obvious dishing and erosion problems in the step S3. As shown in FIG. 10, the polishing result is poor because of an erosion opening 208 and a dishing opening 209.
More related technologies are disclosed in US Patent No. 20020049027. But solutions on how to solve the problems mentioned above are not disclosed.